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3.3 GHz Ultralow Distortion RF/IF Differential Amplifier ADL5562
FEATURES
-3 dB bandwidth of 3.3 GHz (AV = 6 dB) Pin-strappable gain adjust: 6 dB, 12 dB, 15.5 dB Differential or single-ended input to differential output Low noise input stage: 2.1 nV/Hz RTI @ AV = 12 dB Low broadband distortion (Av = 6 dB) 10 MHz: -91 dBc HD2, -98 dBc HD3 70 MHz: -102 dBc HD2, -90 dBc HD3 140 MHz: -104 dBc HD2, -87 dBc HD3 250 MHz: -80 dBc HD2, -94 dBc HD3 IMD3s of -94 dBc at 250 MHz center Slew rate: 9.8 V/ns Fast settling of 2 ns and overdrive recovery of 3 ns Single-supply operation: 3 V to 3.6 V Power-down control Fabricated using the high speed XFCB3 SiGe process
FUNCTIONAL BLOCK DIAGRAM
VCC RF ENBL VIP2 VIP1 VIN1 VIN2 RG2 RG1 RG1 RG2 VON
VCOM
VOP
GND
Figure 1.
APPLICATIONS
Differential ADC drivers Single-ended to differential conversion RF/IF gain blocks SAW filter interfacing
GENERAL DESCRIPTION
The ADL5562 is a high performance differential amplifier optimized for RF and IF applications. The amplifier offers low noise of 2.1 nV/Hz and excellent distortion performance over a wide frequency range, making it an ideal driver for high speed 8-bit to 16-bit ADCs. The ADL5562 provides three gain levels of 6 dB, 12 dB, and 15.5 dB through a pin-strappable configuration. For the singleended input configuration, the gains are reduced to 5.6 dB, 11.1 dB, and 14.1 dB. Using an external series input resistor expands the amplifier gain flexibility and allows for any gain selection from 0 dB to 15.5 dB. The quiescent current of the ADL5562 is typically 80 mA and, when disabled, consumes less than 3 mA, offering excellent input-to-output isolation. The device is optimized for wideband, low distortion performance. These attributes, together with its adjustable gain capability, make this device the amplifier of choice for general-purpose IF and broadband applications where low distortion, noise, and power are critical. This device is optimized for the best combination of slew speed, bandwidth, and broadband distortion. These attributes allow it to drive a wide variety of ADCs and make it ideally suited for driving mixers, pin diode attenuators, SAW filters, and multielement discrete devices. Fabricated on an Analog Devices, Inc., high speed SiGe process, the ADL5562 is supplied in a compact 3 mm x 3 mm, 16-lead LFCSP package and operates over the temperature range of -40C to + 85C.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2009 Analog Devices, Inc. All rights reserved.
08003-001
RF
ADL5562
ADL5562 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications ....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Absolute Maximum Ratings............................................................ 6 ESD Caution .................................................................................. 6 Pin Configuration and Function Descriptions ............................. 7 Typical Performance Characteristics ............................................. 8 Circuit Description ......................................................................... 13 Basic Structure ............................................................................ 13 Applications Information .............................................................. 14 Basic Connections ...................................................................... 14 Input and Output Interfacing ................................................... 15 Gain Adjustment and Interfacing ............................................ 16 ADC Interfacing ......................................................................... 16 Layout Considerations ............................................................... 18 Soldering Information ............................................................... 19 Evaluation Board ........................................................................ 19 Outline Dimensions ....................................................................... 21 Ordering Guide .......................................................................... 21
REVISION HISTORY
9/09--Rev. 0 to Rev. A Changes to Features Section............................................................ 1 Changes to Table 1 ............................................................................ 3 Changes to Figure 5 .......................................................................... 8 Changes to Figure 9 and Figure 10 ................................................. 9 Changes to Figure 32, Equation 1, and Figure 34....................... 15 Changes to Equation 2 ................................................................... 16 Changes to Figure 38, Figure 39, Figure 40, and Table 9 ........... 17 Changes to Figure 43 ...................................................................... 19 Moved Table 14 to .......................................................................... 19 5/09--Revision 0: Initial Version
Rev. A | Page 2 of 24
ADL5562 SPECIFICATIONS
VCC = 3.3 V, VCOM = 1.65 V, RL = 200 differential, AV = 6 dB, CL = 1 pF differential, f = 140 MHz, TA = 25C. Table 1.
Parameter DYNAMIC PERFORMANCE -3 dB Bandwidth Conditions AV = 6 dB, VOUT 1.0 V p-p AV = 12 dB, VOUT 1.0 V p-p AV = 15.5 dB, VOUT 1.0 V p-p AV = 6 dB, VOUT 1.0 V p-p AV = 12 dB, VOUT 1.0 V p-p AV = 15.5 dB, VOUT 1.0 V p-p AV = 6 dB, RL = open AV = 12 dB, RL = open AV = 15.5 dB, RL = open VCC 5% -40C to +85C, AV = 15.5 dB Rise, AV = 15.5 dB, RL = 200 , VOUT = 2 V step Fall, AV = 15.5 dB, RL = 200 , VOUT = 2 V step 2 V step to 1% VIN = 4 V to 0 V step, VOUT 10 mV Min Typ 3300 3900 1900 220 270 270 0.17 0.05 0.06 -0.005 0.32 9.8 10.1 2 3 60 VCC/2 1.4 to 1.8 4.9 60 285 1 65 15 3 400 200 133 307 179 132 0.3 12 3 Device disabled, ENBL low Device enabled, ENBL high ENBL high ENBL low ENBL high ENBL low 3.3 0.6 1.3 -27 -300 80 3.5 3.6 Max Unit MHz MHz MHz MHz MHz MHz dB dB dB dB/V mdB/C V/ns V/ns ns ns dB V V V p-p mV V/C mV dB V/C A pF V V V A A mA mA
Bandwidth for 0.1 dB Flatness
Gain Accuracy
Gain Supply Sensitivity Gain Temperature Sensitivity Slew Rate Settling Time Overdrive Recovery Time Reverse Isolation (S12) INPUT/OUTPUT CHARACTERISTICS Output Common Mode Voltage Adjustment Range Maximum Output Voltage Swing Output Common-Mode Offset Output Common-Mode Drift Output Differential Offset Voltage CMRR Output Differential Offset Drift Input Bias Current Input Resistance (Differential)
1 dB compressed Referenced to VCC/2 -40C to +85C
-40C to +85C AV = 6 dB AV = 12 dB AV = 15.5 dB AV = 5.6 dB, RS = 50 AV = 11.1 dB, RS = 50 AV = 14.1 dB, RS = 50
Input Resistance (Single-Ended) 1
Input Capacitance (Single-Ended) Output Resistance (Differential) POWER INTERFACE Supply Voltage ENBL Threshold ENBL Input Bias Current Quiescent Current
75.5
84.5
Rev. A | Page 3 of 24
ADL5562
Parameter 10 MHz NOISE/HARMONIC PERFORMANCE Second/Third Harmonic Distortion Conditions AV = 6 dB, RL = 200 , VOUT = 2 V p-p AV = 12 dB, RL = 200 , VOUT = 2 V p-p AV = 15.5 dB, RL = 200 , VOUT = 2 V p-p AV = 6 dB, RL = 200 , VOUT = 2 V p-p composite (2 MHz spacing) AV = 12 dB, RL = 200 , VOUT = 2 V p-p composite (2 MHz spacing) AV = 15.5 dB, RL = 200 , VOUT = 2 V p-p composite (2 MHz spacing) AV = 6 dB AV = 12 dB AV = 15.5 dB AV = 6 dB AV = 12 dB AV = 15.5 dB AV = 6 dB, RL = 200 , VOUT = 2 V p-p AV = 12 dB, RL = 200 , VOUT = 2 V p-p AV = 15.5 dB, RL = 200 , VOUT = 2 V p-p AV = 6 dB, RL = 200 , VOUT = 2 V p-p composite (2 MHz spacing) AV = 12 dB, RL = 200 , VOUT = 2 V p-p composite (2 MHz spacing) AV = 15.5 dB, RL = 200 , VOUT = 2 V p-p composite (2 MHz spacing) AV = 6 dB AV = 12 dB AV = 15.5 dB AV = 6 dB AV = 12 dB AV = 15.5 dB AV = 6 dB, RL = 200 , VOUT = 2 V p-p AV = 12 dB, RL = 200 , VOUT = 2 V p-p AV = 15.5 dB, RL = 200 , VOUT = 2 V p-p AV = 6 dB, RL = 200 , VOUT = 2 V p-p composite (2 MHz spacing) AV = 12 dB, RL = 200 , VOUT = 2 V p-p composite (2 MHz spacing) AV = 15.5 dB, RL = 200 , VOUT = 2 V p-p composite (2 MHz spacing) AV = 6 dB AV = 12 dB AV = 15.5 dB AV = 6 dB AV = 12 dB AV = 15.5 dB Min Typ -91/-98 -95/-98 -96/-92 +42/-97 +43/-93 +43/-91 3 2.1 1.6 19.7 19.6 18.2 -102/-90 -97/-85 -93/-83 +46/-96 +44/-93 +43/-91 3 2.1 1.6 19.6 19.6 18.2 -104/-87 -82/-81 -80/-80 +47/-100 +45/-95 +43/-92 3 2.1 1.6 19.6 19.4 18.1 Max Unit dBc dBc dBc dBm/dBc dBm/dBc dBm/dBc nV/Hz nV/Hz nV/Hz dBm dBm dBm dBc dBc dBc dBm/dBc dBm/dBc dBm/dBc nV/Hz nV/Hz nV/Hz dBm dBm dBm dBc dBc dBc dBm/dBc dBm/dBc dBm/dBc nV/Hz nV/Hz nV/Hz dBm dBm dBm
Output Third-Order Intercept/Third-Order Intermodulation Distortion
Noise Spectral Density (RTI)
1 dB Compression Point (RTO)
70 MHz NOISE/HARMONIC PERFORMANCE Second/Third Harmonic Distortion
Output Third-Order Intercept/Third-Order Intermodulation Distortion
Noise Spectral Density (RTI)
1 dB Compression Point (RTO)
140 MHz NOISE/HARMONIC PERFORMANCE Second/Third Harmonic Distortion
Output Third-Order Intercept/Third-Order Intermodulation Distortion
Noise Spectral Density (RTI)
1 dB Compression Point (RTO)
Rev. A | Page 4 of 24
ADL5562
Parameter 250 MHz NOISE/HARMONIC PERFORMANCE Second/Third Harmonic Distortion Conditions AV = 6 dB, RL = 200 , VOUT = 2 V p-p AV = 12 dB, RL = 200 , VOUT = 2 V p-p AV = 15.5 dB, RL = 200 , VOUT = 2 V p-p AV = 6 dB, RL = 200 , VOUT = 2 V p-p composite (2 MHz spacing) AV = 12 dB, RL = 200 , VOUT = 2 V p-p composite (2 MHz spacing) AV = 15.5 dB, RL = 200 , VOUT = 2 V p-p composite (2 MHz spacing) AV = 6 dB AV = 12 dB AV = 15.5 dB AV = 6 dB AV = 12 dB AV = 15.5 dB AV = 6 dB, RL = 200 , VOUT = 1 V p-p AV = 12 dB, RL = 200 , VOUT = 1 V p-p AV = 15.5 dB, RL = 200 , VOUT = 1 V p-p AV = 6 dB, RL = 200 , VOUT = 1 V p-p composite (2 MHz spacing) AV = 12 dB, RL = 200 , VOUT = 1 V p-p composite (2 MHz spacing) AV = 15.5 dB, RL = 200 , VOUT = 1 V p-p composite (2 MHz spacing) AV = 6 dB AV = 12 dB AV = 15.5 dB AV = 6 dB AV = 12 dB AV = 15.5 dB AV = 6 dB, RL = 200 , VOUT = 1 V p-p AV = 12 dB, RL = 200 , VOUT = 1 V p-p AV = 15.5 dB, RL = 200 , VOUT = 1 V p-p AV = 6 dB, RL = 200 , VOUT = 1 V p-p composite (2 MHz spacing) AV = 12 dB, RL = 200 , VOUT = 1 V p-p composite (2 MHz spacing) AV = 15.5 dB, RL = 200 , VOUT = 1 V p-p composite (2 MHz spacing) AV = 6 dB AV = 12 dB AV = 15.5 dB AV = 6 dB AV = 12 dB AV = 15.5 dB Min Typ -80/-94 -74/-86 -74/-84 +43/-94 +41/-87 +40/-86 3.2 2.2 1.6 19.8 19.3 19.1 -75/-69 -69/-73 -72/-75 +40/-98 +39/-97 +38/-93 3.7 2.2 1.6 18.1 18.1 18.1 -70/-60 -69/-61 -66/-59 +24/-65 +24/-66 +25/-66 4.7 2.2 1.6 15 15.1 15.1 Max Unit dBc dBc dBc dBm/dBc dBm/dBc dBm/dBc nV/Hz nV/Hz nV/Hz dBm dBm dBm dBc dBc dBc dBm/dBc dBm/dBc dBm/dBc nV/Hz nV/Hz nV/Hz dBm dBm dBm dBc dBc dBc dBm/dBc dBm/dBc dBm/dBc nV/Hz nV/Hz nV/Hz dBm dBm dBm
Output Third-Order Intercept/Third-Order Intermodulation Distortion
Noise Spectral Density (RTI)
1 dB Compression Point (RTO)
500 MHz NOISE/HARMONIC PERFORMANCE Second/Third Harmonic Distortion
Output Third-Order Intercept/Third-Order Intermodulation Distortion
Noise Spectral Density (RTI)
1 dB Compression Point (RTO)
1000 MHz NOISE/HARMONIC PERFORMANCE Second/Third Harmonic Distortion
Output Third-Order Intercept/Third-Order Intermodulation Distortion
Noise Spectral Density (RTI)
1 dB Compression Point (RTO)
1
See the Applications Information section for a discussion of single-ended input, dc-coupled operation.
Rev. A | Page 5 of 24
ADL5562 ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Supply Voltage (VCC) VIP1, VIP2, VIN1, VIN2 Internal Power Dissipation JA Maximum Junction Temperature Operating Temperature Range Storage Temperature Range Rating 3.6 V VCC + 0.5 V 310 mW 98.3C/W 125C -40C to +85C -65C to +150C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD CAUTION
Rev. A | Page 6 of 24
ADL5562 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
16 GND 15 GND 14 GND 13 GND
VIP2 1 VIP1 2 VIN1 3 VIN2 4
PIN 1 INDICATOR
12 ENBL 11 VOP 10 VON 9 VCOM
ADL5562
TOP VIEW (Not to Scale)
Figure 2. Pin Configuration
Table 3. Pin Function Descriptions
Pin No. 1 2 3 4 5, 6, 7, 8 9 Mnemonic VIP2 VIP1 VIN1 VIN2 VCC VCOM Description Balanced Differential Input. Biased to VCOM, typically ac-coupled. Input for AV = 12 dB gain, strapped to VIP1 for AV = 15.5 dB. Balanced Differential Input. Biased to VCOM, typically ac-coupled. Input for AV = 6 dB gain, strapped to VIP2 for AV = 15.5 dB. Balanced Differential Input. Biased to VCOM, typically ac-coupled. Input for AV = 6 dB gain, strapped to VIN2 for AV = 15.5 dB. Balanced Differential Input. Biased to VCOM, typically ac-coupled. Input for AV = 12 dB gain, strapped to VIN1 for AV = 15.5 dB. Positive Supply. Common-Mode Voltage. A voltage applied to this pin sets the common-mode voltage of the input and output. Typically decoupled to ground with a 0.1 F capacitor. With no reference applied, input and output common mode floats to midsupply (VCC/2). Balanced Differential Output. Biased to VCOM, typically ac-coupled. Balanced Differential Output. Biased to VCOM, typically ac-coupled. Enable. Apply positive voltage (1.0 V < ENBL < VCC) to activate device. Ground. Connect to low impedance ground. Exposed Pad. Connect to a low impedance thermal and electrical ground plane.
10 11 12 13, 14, 15, 16
VON VOP ENBL GND EP
Rev. A | Page 7 of 24
08003-031
NOTES 1. EXPOSED PADDLE. CONNECT TO A LOW IMPEDANCE THERMAL AND ELECTRICAL GROUND PLANE.
VCC 8
VCC 7
VCC 5
VCC 6
ADL5562 TYPICAL PERFORMANCE CHARACTERISTICS
VCC = 3.3 V, VCOM = 1.65 V, RL = 200 differential, AV = 6 dB, CL = 1 pF differential, f = 140 MHz, T = 25C.
16 MAXIMUM GAIN -40C +25C +85C
25 RL = 200
14
20
12 GAIN (dB)
MID GAIN
OP1dB (dBm)
10
15 MIN GAIN +85C MIN GAIN +25C MIN GAIN -40C MID GAIN +85C MID GAIN +25C MID GAIN -40C MAX GAIN +85C MAX GAIN +25C MAX GAIN -40C 0 100 200 300 400 500 600 700 800 900 1000
08003-016
8
10
6
MINIMUM GAIN
100M
1G
10G
FREQUENCY (Hz)
08003-002
4 10M
5
FREQEUNCY (MHz)
Figure 3. Gain vs. Frequency Response for 200 Differential Load, AV = 6 dB, AV = 12 dB, and AV = 15.5 dB over Temperature
20 18 16 14
GAIN (dB)
Figure 6. Output P1dB (OP1dB) vs. Frequency at AV = 6 dB, AV = 12 dB, and AV = 15.5 dB over Temperature, 200 Differential Load
25 RL = 1k
-40C +25C +85C MAXIMUM GAIN OP1dB (dBm)
20
12 10 8 6
MID GAIN
15 MIN GAIN +85C MIN GAIN +25C MIN GAIN -40C MID GAIN +85C MID GAIN +25C MID GAIN -40C MAX GAIN +85C MAX GAIN +25C MAX GAIN -40C
0 100 200 300 400 500 600 700 800 900 1000
08003-017
10
MINIMUM GAIN
100M FREQUENCY (Hz)
1G
10G
08003-003
4 10M
5
FREQUENCY (MHz)
Figure 4. Gain vs. Frequency Response for 1 k Differential Load, AV = 6 dB, AV = 12 dB, and AV = 15.5 dB over Temperature
16 14 12 NOISE FIGURE (dB) 10 8 6 4 2 0 10 AV MAXIMUM AV MID AV MINIMUM
Figure 7. Output P1dB (OP1dB) vs. Frequency at AV = 6 dB, AV = 12 dB, and AV = 15.5 dB over Temperature, 1 k Differential Load
8 7 6 5 4 3 2 1 0 10M
100M FREQUENCY (Hz)
1G
FREQUENCY (MHz)
Figure 5. Noise Figure vs. Frequency at AV = 6 dB, AV = 12 dB, and AV = 15.5 dB
Figure 8. Noise Spectral Density vs. Frequency at AV = 6 dB, AV = 12 dB, and AV = 15.5 dB
Rev. A | Page 8 of 24
08003-005
100
1000
08003-004
NOISE SPECTRAL DENSITY (nV/Hz)
AV MAXIMUM AV MID AV MINIMUM
ADL5562
60 55 50 AV MAXIMUM AV MID AV MINIMUM -40 AV MAXIMUM AV MID AV MINIMUM 0
-60
-20
IMD3, RL = 200 (dBc)
-80
-40
OIP3 (dBm)
40 35 30 25 20 15
08003-018
-100
-60
-120
-80
-140
-100
0
50
100
150
200
250
0
50
100
150
200
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 9. Output Third-Order Intercept at Three Gains, Output Level at 2 V p-p Composite, RL = 200
60 +85C +25C -40C
Figure 12. Two-Tone Output IMD vs. Frequency, Output Level at 2 V p-p Composite, RL = 200 and RL = 1 k
50 45 40 35
OIP3 (dBm)
50
40
OIP3 (dBm)
30 25 20 15 10 5
30
20
10
FREQUENCY (MHz)
POUT/TONE (dBm)
Figure 10. Output Third-Order Intercept vs. Frequency, Over Temperature, Output Level at 2 V p-p Composite, RL = 200
60 AV MAXIMUM AV MID AV MINIMUM
Figure 13. Output Third-Order Intercept (OIP3) vs. Power (POUT), Frequency 140 MHz, AV = 15.5 dB
-70 -75 -80 AV MAXIMUM AV MID AV MINIMUM
55
50
OIP3 (dBm)
-85
IMD (dBc)
45
-90 -95 -100
40
35
-105 -110
0
50
100
150
200
250
08003-006
0
50
100
150
200
250
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 11. OIP3 vs. Frequency (Single-Ended Input)
Figure 14. IMD vs. Frequency (Single-Ended Input)
Rev. A | Page 9 of 24
08003-007
30
08003-028
0
50
100
150
200
250
08003-019
0
0 -2
-1
0
1
2
3
4
5
08003-020
10
-160
-120 250
IMD3, RL = 1k (dBc)
45
ADL5562
-40 AV MAXIMUM AV MID AV MINIMUM 0
-40 AV MAXIMUM AV MID AV MINIMUM
0
HARMONIC DISTORTION HD2 (dBc)
-60
-20
HARMONIC DISTORTION HD3 (dBc)
HARMONIC DISTORTION HD2 (dBc)
-60
-20
-80
-40
-80
-40
-100
-60
-100
-60
-120
-80
-120
-80
-140
-100
-140
-100
08003-021
-160
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 15. Harmonic Distortion (HD2/HD3) vs. Frequency at AV = 6 dB, AV = 12 dB, and AV = 15.5 dB, Output Level at 2 V p-p, RL = 200
-40
+85C +25C -40C
Figure 18. Harmonic Distortion (HD2/HD3) vs. Frequency at Av = 6 dB, Av = 12 dB, and Av = 15.5 dB, Output Level at 2 V p-p, RL = 1 k
-20 -30
0
HARMONIC DISTORTION HD2 (dBc)
-60
-20
HARMONIC DISTORTION HD3 (dBc)
HARMONIC DISTORTION (dBc)
-40 -50 -60 -70 -80 -90
-80
-40
-100
-60
-120
-80
HD2 HD3
-140
-100
08003-022
0
50
100
150
200
-1
0
1
2
3
4
5
FREQUENCY (MHz)
POUT (dBm)
Figure 16. Harmonic Distortion (HD2/HD3) vs. Frequency, Three Temperatures, Output Level at 2 V p-p, RL = 200
-40 +85C +25C -40C 0
Figure 19. Harmonic Distortion (HD2/HD3) vs. Power (POUT), Frequency 140 MHz, AV = 15.5 dB
-60 -65
HARMONIC DISTORTION HD2 (dBc)
-20
HARMONIC DISTORTION HD3 (dBc)
-50 AV MAXIMUM AV MID AV MINIMUM -55 -60 -65 -70 -75 -80 -85 -90 -95 0 50 100 150 200
08003-008
HARMONIC DISTORTION HD2 (dBc)
-70 -75 -80 -85 -90 -95 -100 -105
-80
-40
-100
-60
-120
-80
-140
-100
0
50
100
150
200
FREQUENCY (MHz)
08003-023
-160
-120 250
-110
-100 250
FREQUENCY (MHz)
Figure 17. Harmonic Distortion (HD2/HD3) vs. Frequency, Over Temperature, Output Level at 2 V p-p, RL = 1 k
Figure 20. Harmonic Distortion (HD2/HD3) vs. Frequency (Single-Ended Input)
Rev. A | Page 10 of 24
HARMONIC DISTORTION HD3 (dBc)
-60
08003-029
-160
-120 250
-100 -2
08003-024
0
50
100
150
200
-120 250
-160
0
50
100
150
200
-120 250
HARMONIC DISTORTION HD3 (dBc)
ADL5562
-30 -40 -50 -60 -70 -80 -90 -100 AV MAXIMUM AV MID AV MINIMUM -60 -70 -80 -90 -100 -110 -120 -130 1000
-55 -60
HARMONIC DISTORTION HD2 (dBc)
-60 AV MAXIMUM AV MID AV MINIMUM -65 -70 -75 -80 -85 -90 -95 -100 -105
08003-010
HARMONIC DISTORTION HD2 (dBc)
HARMONIC DISTORTION HD3 (dBc)
-65 -70 -75 -80 -85 -90 -95 -100 -105 1.1 1.2 1.3 1.4 1.5 VCOM (V) 1.6 1.7 1.8
RLOAD ()
Figure 21. Harmonic Distortion (HD2/HD3) vs. RLOAD
1.0 0.9 0.8
08003-009
0
100
200
300
400
500
600
700
800
900
-110 1.9
Figure 24. Harmonic Distortion (HD2/HD3) vs. VCOM
0 AV MAXIMUM AV MID AV MINIMUM -20 -40
GROUP DELAY (ns)
0.6 0.5 0.4 0.3
-80 -100 -120 -140 -160
08003-030
0.2 0.1
0
100
200
300
400
500
600
700
800
900
FREQUENCY (MHz)
Figure 22. ENBL Time Domain Response
110 100 90
VOLTAGE (V)
Figure 25. Group Delay and Phase vs. Frequency
80 RL = 1k AV MAXIMUM AV MID AV MINIMUM 70 60 50 RL = 200 70 60 50 40
08003-036
2V p-p OUTPUT
CMRR (dB)
40 30 20 10 0 1G
100M FREQUENCY (Hz)
Figure 23. Large Signal Pulse Response, AV = 15.5 dB
Figure 26. Common-Mode Rejection Ratio (CMRR) vs. Frequency
Rev. A | Page 11 of 24
08003-012
TIME (2.5ns/DIV)
30 10M
CMRR (dB)
80
08003-011
TIME (2.5ns/DIV)
-180 1000
PHASE (Degrees)
VOLTAGE (V)
0.7
-60
HARMONIC DISTORTION HD3 (dBc)
ADL5562
0 -10
16 14
AV MAXIMUM AV MID AV MINIMUM
16 14 12 10 8 6 4 2 0 1G
-20 -30 -40 -50 -60 -70
DISABLED
12 10 8 6 4 2 0 10M
ENABLED
100M FREEQUENCY (Hz)
FREQUENCY (GHz)
Figure 27. Reverse Isolation (S12) vs. Frequency
1k 900 AV MAXIMUM AV MID AV MINIMUM
20 10
Figure 29. Output Impedance vs. Frequency
700 600 500 400 300 200 100 0 10M 100M FREQUENCY (Hz)
-10 -20 -30 -40 -50 -60 -70
Figure 28. Input Impedance vs. Frequency
Rev. A | Page 12 of 24
08003-014
-80 1G
IMPEDANCE PHASE (Degrees)
IMPEDANCE MAGNITUDE ()
800
0
08003-015
0
0.5
1.0
1.5
2.0
2.5
3.0
08003-013
IMPEDANCE PHASE (Degrees)
IMPEDANCE MAGNITUDE ()
S12 (dB)
ADL5562 CIRCUIT DESCRIPTION
BASIC STRUCTURE
The ADL5562 is a low noise, fully differential amplifier/ADC driver that uses a 3.3 V supply. It provides three gain options (6 dB, 12 dB, and 15.5 dB) without the need for external resistors and has wide bandwidths of 2.6 GHz for 6 dB, 2.3 GHz for 12 dB, and 2.1 GHz for 15.5 dB. Differential input impedance is 400 for 6 dB, 200 for 12 dB, and 133 for 15.5 dB. It has a differential output impedance of 10 and a common-mode adjust voltage of 1.25 V to 1.85 V.
0.1F
+
1/ R 2S
400 VIP2 100 VIP1 200 5
The ADL5562 is composed of a fully differential amplifier with on-chip feedback and feed-forward resistors. The two feed-forward resistors on each input set this pin-strappable amplifier in three different gain configurations of 6 dB, 12 dB, and 15.5 dB. The amplifier is designed to provide high differential open-loop gain and an output common-mode circuit that enables the user to change the common-mode voltage from a VCOM pin. The amplifier is designed to provide superior low distortion at frequencies up to and beyond 300 MHz with low noise and low power consumption. The low distortion and noise are realized with a 3.3 V power supply at 80 mA. The ADL5562 is very flexible in terms of I/O coupling. It can be ac-coupled or dc-coupled at the inputs and/or the outputs within the specified input and output common-mode levels. The input of the device can be configured as single-ended or differential with similar distortion performance. Due to the internal connections between the inputs and outputs, keep the output common-mode voltage between 1.25 V and 1.85 V for the best distortion. For a dc-coupled input, the input common mode should be between 1 V and 2.3 V for the best distortion. The device has been characterized using 2 V p-p into 200 . If the inputs are ac-coupled, the input and output common-mode voltages are set by VCC/2 when no external circuitry is used. The ADL5562 provides an output common-mode voltage set by VCOM, which allows driving an ADC directly without external components, such as a transformer or ac coupling capacitors, provided the VCOM of the amplifier is within the VCOM of the ADC. For dc-coupled requirements, the input VCM must be set by the VCOM pin in all three gain settings.
AC
VIN1 200 VIN2 100 400 0.1F
+
RL 5
08003-032
1/ R 2S
Figure 30. Basic Structure
Rev. A | Page 13 of 24
ADL5562 APPLICATIONS INFORMATION
BASIC CONNECTIONS
Figure 31 shows the basic connections for operating the ADL5562. VCC should be 3.3 V with each supply pin decoupled with at least one low inductance surface-mount ceramic capacitor of 0.1 F placed as close as possible to the device. The VCOM pin (Pin 9) should also be decoupled using a 0.1 F capacitor. The gain of the part is determined by the pin-strappable input configuration. When Input A is applied to VIP1 and Input B is applied to VIN1, the gain is 6 dB (minimum gain, see Equation 1 and Equation 2). When Input A is applied to VIP2 and Input B is applied to VIN2, the gain is 12 dB (middle gain). When Input A is applied to VIP1 and VIP2 and Input B is applied to VIN1 and VIN2, the gain is 15.5 dB (maximum gain). Pin 1 to Pin 4, Pin 10, and Pin 11 are biased at 1/2 VCC above ground and can be dc-coupled (if within the specified input or output common-mode voltage levels) or ac-coupled as shown in Figure 31. To enable the ADL5562, the ENBL pin must be pulled high. Pulling the ENBL pin low puts the ADL5562 in sleep mode, reducing the current consumption to 3 mA at ambient.
VCC
RS/2 BALANCED SOURCE RS/2
A 0.1F
16 GND 1 VIP2
2 VIP1
15 GND
14 GND
13 GND ENBL 12
VOP 11
AC
0.1F B 3 VIN1 4 VIN2
ADL5562
VON 10 VCOM 9
RL
BALANCED LOAD
VCC 5 VCC
10F
VCC 6
VCC 7
0.1F
VCC 8
0.1F
Figure 31. Basic Connections
Rev. A | Page 14 of 24
08003-033
ADL5562
INPUT AND OUTPUT INTERFACING
The ADL5562 can be configured as a differential-input to differential-output driver, as shown in Figure 32. The differential broadband input is provided by the ETC1-1-13 balun transformer, and the two 34.8 resistors provide a 50 input match for the three input impedances that change with the variable gain strapping. The input and output 0.1 F capacitors isolate the VCC/2 bias from the source and balanced load. The load should equal 200 to provide the expected ac performance (see the Specifications section and the Typical Performance Characteristics section).
3.3V VIP2 VIP1 VIN1 B VIN2 0.1F 0.1F
Single-Ended Input to Differential Output
The ADL5562 can also be configured in a single-ended input to differential output driver, as shown in Figure 34. In this configuration, the gain of the part is reduced due to the application of the signal to only one side of the amplifier. The strappable gain values are listed in Table 6 with the required terminations to match to a 50 source using R1 and R2. Note that R1 must equal the parallel value of the source and R2. The input and output 0.1 F capacitors isolate the VCC/2 bias from the source and the balanced load. The performance for this configuration is shown in Figure 11, Figure 14, and Figure 20.
3.3V 0.1F
ETC1-1-13 50 AC R2
0.1F
A
+
RL 2 RL 2
50 AC R2
0.1F
A
VIP2 VIP1 VIN1
0.1F
+ +
R1
+
RL 2 RL 2
+
B + R1
08003-043
VIN2
0.1F
NOTES 1. FOR 6dB GAIN (AV = 2), CONNECT INPUT A TO VIP1 AND INPUT B TO VIN1. 2. FOR 12dB GAIN (AV = 4), CONNECT INPUT A TO VIP2 AND INPUT B TO VIN2. 3. FOR 15.5dB GAIN (AV = 6), CONNECT INPUT A TO BOTH VIP1 AND VIP2 AND INPUT B TO BOTH VIN1 AND VIN2.
Figure 32. Differential-Input to Differential-Output Configuration
Table 4. Differential Termination Values for Figure 32
Gain (dB) 6 12 15.5 R1 () 28.7 33.2 40.2 R2 () 28.7 33.2 40.2
Figure 34. Single-Ended Input to Differential Output Configuration
Table 6. Single-Ended Termination Values for Figure 34
Gain (dB) 5.6 11.1 14.1 R1 () 27 29 30 R2 () 60 69 77
The differential gain of the ADL5562 is dependent on the source impedance and load, as shown in Figure 33.
0.1F 400 VIP2 100 VIP1 200 5 0.1F
1/
2
RS
The single-ended gain configuration of the ADL5562 is dependent on the source impedance and load, as shown in Figure 35.
RL 2 RL 2
RS AC + R1 0.1F R2 0.1F VIP2 100 VIP1 200 VIN1 200 VIN2 100 400
08003-046
AC
VIN1 200 VIN2 100 5 400 0.1F
400 5 0.1F
1/
2 RS
08003-045
+
+
0.1F
NOTES 1. FOR 5.6dB GAIN (AV = 1.9), CONNECT INPUT A TO VIP1 AND INPUT B TO VIN1. 2. FOR 11.1dB GAIN (AV = 3.6), CONNECT INPUT A TO VIP2 AND INPUT B TO VIN2. 3. FOR 14.1dB GAIN (AV = 5.1), CONNECT INPUT A TO BOTH VIP1 AND VIP2 AND INPUT B TO BOTH VIN1 AND VIN2.
0.1F
08003-044
The differential gain can be determined using the following formula. The values of RIN for each gain configuration are shown in Table 5.
+ + + +
+
RL 2 RL 2
+
5
0.1F
+
Figure 33. Differential Input Loading Circuit
Figure 35. Single-Ended Input Loading Circuit
AV =
400 RL x RIN 10 + RL
(1)
Table 5. Values of RIN for Differential Gain
Gain (dB) 6 12 15.5 RIN () 200 100 66.7
Rev. A | Page 15 of 24
ADL5562
The single-ended gain can be determined using the following formula. The values of RIN and RX for each gain configuration are shown in Table 7.
R + RS R2 RL 400 AV 1 = x xX x RX RS x R2 RS + R2 10 + RL RIN + R + R2 S
Table 7. Values of RIN and RX for Single-Ended Gain
Gain (dB) 5.6 11.1 14.1
1
The necessary shunt component, RSHUNT, to match to the source impedance, RS, can be expressed as
RSHUNT =
(2)
1 1 1 - RS RSERIES + RIN
(4)
RIN () 200 100 66.7
RX () R2 || 3071 R2 || 1791 R2 || 1321
The insertion loss and the resultant power gain for multiple shunt resistor values are summarized in Table 8. The source resistance and input impedance need careful attention when using Equation 3 and Equation 4. The reactance of the input impedance of the ADL5562 and the ac coupling capacitors must be considered before assuming that they make a negligible contribution.
Table 8. Gain Adjustment Using Series Resistor
Il (dB) 2 4 2 4 2 2 4 2 4 2 4 2 RIN () 400 400 200 200 133 400 400 200 200 400 400 200 RS () 50 50 50 50 50 200 200 200 200 50 50 50 RSERIES () 105 232 51.1 115 34.8 102 232 51.1 115 105 232 51.1 RSHUNT () 54.9 54.9 61.9 59 71.5 332 294 976 549 54.9 54.9 61.9
These values based on a 50 input match.
GAIN ADJUSTMENT AND INTERFACING
The effective gain of the ADL5562 can be reduced using a number of techniques. A matched attenuator network can reduce the effective gain; however, this requires the addition of a separate component that can be prohibitive in size and cost. Instead, a simple voltage divider can be implemented using the combination of additional series resistors at the amplifier input and the input impedance of the ADL5562, as shown in Figure 36. A shunt resistor is used to match to the impedance of the previous stage.
1/ R 2S
0.1F 1/2 RSERIES
1/ R 2 SHUNT
VIN1 VIN2
AC
1/ R 2S
0.1F 1/2 RSERIES
1/ R 2 SHUNT
VIP1 VIP2
ADL5562
08003-037
ADC INTERFACING
The ADL5562 is a high output linearity amplifier that is optimized for ADC interfacing. There are several options available to the designer when using the ADL5562. Figure 37 shows a simplified wideband interface with the ADL5562 driving the AD9445. The AD9445 is a 14-bit, 125 MSPS ADC with a buffered wideband input. For optimum performance, the ADL5562 should be driven differentially using an input balun. Figure 37 uses a wideband 1:1 transmission line balun followed by two 34.8 resistors in parallel with the three input impedances (which change with the gain selection of the AD55L62) to provide a 50 differential input impedance. This provides a wideband match to a 50 source. The ADL5562 is ac-coupled from the AD9445 to avoid commonmode dc loading. The 33 series resistors help to improve the isolation between the ADL5562 and any switching currents present at the analog-to-digital sample-and-hold input circuitry. The AD9445 input presents a 2 k differential load impedance and requires a 2 V p-p differential input swing to reach full scale (VREF = 1 V).
3.3V VIP2 VIP1 VIN1 VIN2 VOP
Figure 36. Gain Adjustment Using a Series Resistor
Figure 36 shows a typical implementation of the divider concept that effectively reduces the gain by adding attenuation at the input. For frequencies less than 100 MHz, the input impedance of the ADL5562 can be modeled as a real 133 , 200 , or 400 resistance (differential) for maximum, middle, and minimum gains, respectively. Assuming that the frequency is low enough to ignore the shunt reactance of the input and high enough so that the reactance of moderately sized ac coupling capacitors can be considered negligible, the insertion loss, Il, due to the shunt divider can be expressed as
RIN Il(dB) = 20 log R SERIES + RIN

(3)
50 AC
ETC1-1-13 34.8
0.1F A
0.1F
+
33
VIN+ 14-BIT ADC VIN-
0.1F B
ADL5562
VON
AD9445
14
+ +
0.1F
+
33
Figure 37. Wideband ADC Interfacing Example Featuring the AD9445
Rev. A | Page 16 of 24
08003-038
34.8
ADL5562
This circuit provides variable gain, isolation, and source matching for the AD9445. Using this circuit with the ADL5562 in a gain of 6 dB, an SFDR performance of 87 dBc is achieved at 140 MHz, and a -3 dB bandwidth of 760 MHz, as indicated in Figure 38 and Figure 39.
0 -10 -20 -30 -40 -50 -60 ADL5562 DRIVING THE AD9445 14-BIT ADC GAIN = 6dB INPUT = 140MHz SNR = 66.25dBc SFDR = 87.44dBc NOISE FLOOR = -109.5dB FUND = -1.081dBFS SECOND = -84.54dBc THIRD = -84.54dBc
The wideband frequency response is an advantage in broadband applications, such as predistortion receiver designs and instrumentation applications. However, by designing for a wide analog input frequency range, the cascaded SNR performance is somewhat degraded due to high frequency noise aliasing into the wanted Nyquist zone. An alternative narrow-band approach is presented in Figure 40. By designing a narrow band-pass antialiasing filter between the ADL5562 and the target ADC, the output noise of the ADL5562 outside of the intended Nyquist zone can be attenuated, helping to preserve the available SNR of the ADC. In general, the SNR improves several decibels when including a reasonable order antialiasing filter. In this example, a low loss 1:1 input transformer is used to match the ADL5562 balanced input to a 50 unbalanced source, resulting in minimum insertion loss at the input. Figure 40 is optimized for driving some of the Analog Devices popular unbuffered ADCs, such as the AD9246, AD9640, and AD6655. Table 9 includes antialiasing filter component recommendations for popular IF sampling center frequencies. Inductor L5 works in parallel with the on-chip ADC input capacitance and a portion of the capacitance presented by C4 to form a resonant tank circuit. The resonant tank helps to ensure that the ADC input looks like a real resistance at the target center frequency. The L5 inductor shorts the ADC inputs at dc, which introduces a zero into the transfer function. In addition, the ac coupling capacitors introduce additional zeros into the transfer function. The final overall frequency response takes on a bandpass characteristic, helping to reject noise outside of the intended Nyquist zone. Table 9 provides initial suggestions for prototyping purposes. Some empirical optimization may be needed to help compensate for actual PCB parasitics.
(dBFS)
-70 -80 -90 -100 -110 -120 -130 -140 -150
08003-026
0
6.25 12.50 18.75 25.00 31.25 37.50 43.75 50.00 56.25 62.50
FREQUENCY (MHz)
Figure 38. Measured Single-Tone Performance of the Circuit in Figure 37 for a 100 MHz Input Signal
0 -1 -2 -3 -4
(dBFS)
-5 -6 -7 -8 -9 -10 2.00 FIRST POINT = -1.02dBFS END POINT = -5.69dBFS MID POINT = -1.09dBFS MIN = -5.69dBFS MAX = -0.88dBFS 81.90
08003-025
161.80 321.60 481.40 641.20 801.00 241.70 401.50 561.30 721.10 FREQUENCY (MHz)
Figure 39. Measured Frequency Response of the Wideband ADC Interface Depicted in Figure 37
1nF 4 L1 L3 105
1nF 4
L1
L3
105
Figure 40. Narrow-Band IF Sampling Solution for an Unbuffered ADC Application
Table 9. Interface Filter Recommendations for Various IF Sampling Frequencies
Center Frequency (MHz) 96 140 170 211 1 dB Bandwidth (MHz) 30 33 32 33 L1 (nH) 3.3 3.3 3.3 3.3 C2 (pF) 47 47 56 47 L3 (nH) 27 27 27 27 C4 (pF) 75 33 22 18 L5 (nH) 100 120 110 56
Rev. A | Page 17 of 24
08003-039
ADL5562
C2
C4
CML
L5
AD9246 AD9640 AD6655
ADL5562
LAYOUT CONSIDERATIONS
High-Q inductive drives and loads, as well as stray transmission line capacitance in combination with package parasitics, can potentially form a resonant circuit at high frequencies, resulting in excessive gain peaking or possible oscillation. If RF transmission lines connecting the input or output are used, they should be designed such that stray capacitance at the input/output pins is
R3 R1 ETC1-1-13 0.1F R4 VIP2 0.1F VIP1 VOP R7 ETC1-1-13 SPECTRUM ANALYZER
minimized. In many board designs, the signal trace widths should be minimal where the driver/receiver is more than oneeighth of the wavelength from the amplifier. This nontransmission line configuration requires that underlying and adjacent ground and low impedance planes be dropped from the signal lines
R9
ADL5562
R5 VIN1 R2 0.1F R6 VIN2 VON 0.1F R10 R8
Figure 41. General Purpose Characterization Circuit
Table 10. Gain Setting and Input Termination Components for Figure 41
AV (dB) 6 12 15.5 R1 () 29 33 40.2 R2 () 29 33 40.2 R3 () Open 0 0 R4 () 0 Open 0 R5 () 0 Open 0 R6 () Open 0 0
Table 11. Output Matching Network for Figure 41
RL () 200 1k R7 () 84.5 487 R8 () 84.5 487 R9 () 34.8 25 R10 () 34.8 25
R3 R1 PORT 1 R4
VIP2 VIP1 VOP R7
R9 PORT 2
ADL5562
PORT 3 R2 R5 VIN1 R6 VIN2 VON R10
08003-035
R8
PORT 4
Figure 42. Differential Characterization Circuit Using Agilent E8357A 4-Port PNA
Table 12. Gain Setting and Input Termination Components for Figure 42
AV (dB) 6 12 15.5 R1 () 67 100 200 R2 () 67 100 200 R3 () Open 0 0 R4 () 0 Open 0 R5 () 0 Open 0 R6 () Open 0 0
Table 13. Output Matching Network for Figure 42
RL () 200 1k R7 () 50 475 R8 () 50 475 R9 () Open 61.9 R10 () Open 61.9
Rev. A | Page 18 of 24
08003-034
ADL5562
SOLDERING INFORMATION
On the underside of the chip scale package, there is an exposed compressed paddle. This paddle is internally connected to the ground of the chip. Solder the paddle to the low impedance ground plane on the PCB to ensure the specified electrical performance and to provide thermal relief. To further reduce thermal impedance, it is recommended that the ground planes on all layers under the paddle be stitched together with vias. To realize the minimum gain (6 dB into a 200 load), Input 1 (VIN1 and VIP1) must be used by installing 0 resistors at R3 and R4, leaving R5 and R6 open. R1 and R2 must be 33 for a 50 input impedance. Likewise, driving Input 2 (VIN2 and VIP2) realizes the middle gain (12 dB into a 200 load) by installing 0 at R5 and R6 and leaving R3 and R4 open. R1 and R2 must be 29 for a 50 input impedance. For the maximum gain (15.5 dB into a 200 load), both inputs are driven by installing 0 resistors at R3, R4, R5, and R6. R1 and R2 must be 40.2 for a 50 input impedance. The balanced input and output interfaces are converted to single ended with a pair of baluns (M/A-COM ETC1-1-13). The balun at the input, T1, provides a 50 single-ended-todifferential transformation. The output balun, T2, and the matching components are configured to provide a 200 to 50 impedance transformation with an insertion loss of about 17 dB.
GND 16 GND C1 0.01F R1 49.9 C12 0.1F R2 49.9 C2 0.01F R5 0 R3 0 R4 0 R6 0 VPOS C3 10F 1 2 3 4 VIP2 VIP1 15 GND 14 GND 13 GND ENBL 12 VOP 11 C9 0.01F C10 0.01F C11 0.1F J2 ENBL C8 0.1F T2 R9 84.5 R10 84.5 C13 0.1F R11 OPEN J3
EVALUATION BOARD
Figure 43 shows the schematic of the ADL5562 evaluation board. The board is powered by a single supply in the 3 V to 3.6 V range. The power supply is decoupled by 10 F and 0.1 F capacitors. Table 14 details the various configuration options of the evaluation board. Figure 44 and Figure 45 show the component and circuit layouts of the evaluation board.
VPOS P1 AGND R7 34.8 R8 34.8
J1
T1
ADL5562
VIN1 VIN2 VCC 5 VON 10 VOCM 9 VCC 8
VCC 6
VCC 7
Figure 43. Evaluation Board Schematic
Table 14. Evaluation Board Configuration Options
Component VPOS, GND C3, C4, C5, C6, C7, C11 J1, R1, R2, R3, R4, R5, R6, C1, C2, C12, T1 Description Ground and supply vector pins. Power supply decoupling. The supply decoupling consists of a 10 F capacitor (C3) to ground. C4 to C7 are bypass capacitors. C11 ac couples VREF to ground. Input interface. The SMA labeled J1 is the input. T1 is a 1-to-1 impedance ratio balun to transform a single-ended input into a balanced differential signal. C1 and C2 provide ac coupling. C12 is a bypass capacitor. R1 and R2 provide a differential 50 input termination. R3 to R6 are used to select the input for the pin-strappable gain. Maximum gain: R3, R4, R5, R6 = 0 ; and R1, R2 = 40.2 . Middle gain: R5, R6 = 0 ; and R3, R4 = open; R1, R2 = 33 . Minimum gain: R3, R4 = 0 ; and R5, R6 = open; R1, R2 = 29 . Output interface. The SMA labeled J3 is the output. T2 is a 1-to-1 impedance ratio balun to transform a balanced differential signal to a single-ended signal. C13 is a bypass capacitor. R7, R8, R9, and R10 are provided for generic placement of matching components. The evaluation board is configured to provide a 200 to 50 impedance transformation with an insertion loss of 17 dB. C9 and C10 provide ac coupling. Default Condition VPOS, GND = installed C3 = 10 F (Size D), C4, C5, C6, C7, C11 = 0.1 F (Size 0402) J1 = installed, R1, R2 = 40.2 (Size 0402), R3, R4, R5, R6 = 0 (Size 0402), C1, C2 = 0.01 F (Size 0402), C12 = 0.1 F (Size 0402) T1 = ETC1-1-13 (M/A-COM) J3 = installed, R7, R8 = 84.5 (Size 0402), R9, R10 = 34.8 (Size 0402), R11 = open (Size 0402), C9, C10 = 0.01 F (Size 0402), C13 = 0.1 F (Size 0402) T2 = ETC1-1-13 (M/A-COM) ENBL, P1= installed, C8 = 0.1 F (Size 0402)
J3, R7, R8, R9, R10, R11, C9, C10, C13, T2
ENBL, P1, C8
Device enable. C8 is a bypass capacitor. When the P1 jumper is set toward the VPOS label, the ENBL pin is connected to the supply, enabling the device. In the opposite direction, toward the GND label, the ENBL pin is grounded, putting the device in power-down mode.
Rev. A | Page 19 of 24
08003-040
C4 0.1F
C5 0.1F
C6 0.1F
C7 0.1F
ADL5562
08003-041
Figure 44. Layout of Evaluation Board, Component Side
Figure 45. Layout of Evaluation Board, Circuit Side
Rev. A | Page 20 of 24
08003-042
ADL5562 OUTLINE DIMENSIONS
5.00 BSC SQ 0.60 MAX 0.60 MAX
15 16 20 1
PIN 1 INDICATOR
3.20 3.10 SQ 3.00
5
PIN 1 INDICATOR
4.75 BSC SQ
0.65 BSC
EXPOSED PAD
(BOTTOM VIEW)
TOP VIEW 0.70 0.65 0.60
0.75 0.60 0.50
11
10
6
2.60 BSC FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET.
0.90 0.85 0.80 SEATING PLANE
12 MAX
COMPLIANT TO JEDEC STANDARDS MO-220-VHHC
Figure 46. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 3 mm x 3 mm Body, Very Thin Quad (CP-16-2) Dimensions shown in millimeters
ORDERING GUIDE
Model ADL5562ACPZ-R7 1 ADL5562ACPZ-WP1 ADL5562-EVALZ1
1
Temperature Range -40C to +85C -40C to +85C
Package Description 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ], 7" Reel 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ], Waffle Pack Evaluation Board
Package Option CP-16-2 CP-16-2
042209-B
0.35 0.28 0.23
0.05 MAX 0.01 NOM COPLANARITY 0.05 0.20 REF
Branding Q1Q Q1Q
Ordering Quantity 1,500 64
Z = RoHS Compliant Part.
Rev. A | Page 21 of 24
ADL5562 NOTES
Rev. A | Page 22 of 24
ADL5562 NOTES
Rev. A | Page 23 of 24
ADL5562 NOTES
(c)2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08003-0-9/09(A)
Rev. A | Page 24 of 24

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